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A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.


Decrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
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f4-sensors-12-03587: Decrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.

Mentions: On the contrary, if a higher voltage is applied to the non-black bar side, then, the memristance is decreased. We call this configuration the decrementally biased memristor. By adding a voltage inverter after the voltage multiplier as shown in Figure 4, the decrementally biased memristor can be implemented. The input voltage in the decrementally biased memristor is given by:vin =(Rs′−qCC×RT)iin.


A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Decrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376599&req=5

f4-sensors-12-03587: Decrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
Mentions: On the contrary, if a higher voltage is applied to the non-black bar side, then, the memristance is decreased. We call this configuration the decrementally biased memristor. By adding a voltage inverter after the voltage multiplier as shown in Figure 4, the decrementally biased memristor can be implemented. The input voltage in the decrementally biased memristor is given by:vin =(Rs′−qCC×RT)iin.

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.