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A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.


incrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
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f3-sensors-12-03587: incrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.

Mentions: Figure 3 shows the schematic of the incrementally biased memristor emulator where memristance increases when a positive voltage vin applied at the input terminal. The input voltage applied at a memristor emulator is converted into an input current iin with a resistor Rs and op Amp U0 via the virtual ground constraint. Since the current iin is used at several places, its replicas are generated using current mirrors. Observe that a current mirror copies single directional current only. For bi-directional (positive and negative) currents, iin must be separated into a positive part and a negative part and processed separately at different parts of the circuit. In the circuit of Figure 3, the positive part of the current, duplicated by a current mirror MN0 and MN2 is fed into a resistor RT and a capacitor C by current mirror MP3 and MP4 with couple of MP1 respectively. On the other hand, MP0 and MP2 acts as the negative part of current mirror that flows out from resistor RT and capacitor C by current mirror MN3 and MN4 which are coupled with MN1.


A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

incrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376599&req=5

f3-sensors-12-03587: incrementally-biased memristor emulator circuit (a) memristor emulator circuit; (b) a schematic of memristor emulator.
Mentions: Figure 3 shows the schematic of the incrementally biased memristor emulator where memristance increases when a positive voltage vin applied at the input terminal. The input voltage applied at a memristor emulator is converted into an input current iin with a resistor Rs and op Amp U0 via the virtual ground constraint. Since the current iin is used at several places, its replicas are generated using current mirrors. Observe that a current mirror copies single directional current only. For bi-directional (positive and negative) currents, iin must be separated into a positive part and a negative part and processed separately at different parts of the circuit. In the circuit of Figure 3, the positive part of the current, duplicated by a current mirror MN0 and MN2 is fed into a resistor RT and a capacitor C by current mirror MP3 and MP4 with couple of MP1 respectively. On the other hand, MP0 and MP2 acts as the negative part of current mirror that flows out from resistor RT and capacitor C by current mirror MN3 and MN4 which are coupled with MN1.

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.