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A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.


Synaptic multiplication with (a) Gilbert multiplier-based circuit [10,16]; (b) memristor based circuit.
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f11-sensors-12-03587: Synaptic multiplication with (a) Gilbert multiplier-based circuit [10,16]; (b) memristor based circuit.

Mentions: Simulations of the synaptic weight processing were also conducted with our memrisor emulator-based bridge synapse. Figure 11(b) shows the linearity of the relationship between the input voltages, and the output of the memristor emulator-based bridge synapse. The weighting factor ξ is in the range [−0.1,0.1] when synaptic input range is [−1,1] V. The performance of the conventional analog multiplication (synaptic weight) circuit employed in the programmable analog vector matrix multiplication and CNN [10,16] is shown in Figure 11(a). As in the Figure 11(a), the linear region on the function of input-output relation is quite narrow and the intervals between graphs are not quite uniform. However, in the case of memristor bridge synapse, the linear regions are very wide and the intervals between graphs are uniform as in Figure 11(b). The linearity of the memristor bridge synaptic circuit comes from the linear weight assignment at the memristor bridge synapse and the operation at the middle of the memristor dynamic range.


A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Synaptic multiplication with (a) Gilbert multiplier-based circuit [10,16]; (b) memristor based circuit.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376599&req=5

f11-sensors-12-03587: Synaptic multiplication with (a) Gilbert multiplier-based circuit [10,16]; (b) memristor based circuit.
Mentions: Simulations of the synaptic weight processing were also conducted with our memrisor emulator-based bridge synapse. Figure 11(b) shows the linearity of the relationship between the input voltages, and the output of the memristor emulator-based bridge synapse. The weighting factor ξ is in the range [−0.1,0.1] when synaptic input range is [−1,1] V. The performance of the conventional analog multiplication (synaptic weight) circuit employed in the programmable analog vector matrix multiplication and CNN [10,16] is shown in Figure 11(a). As in the Figure 11(a), the linear region on the function of input-output relation is quite narrow and the intervals between graphs are not quite uniform. However, in the case of memristor bridge synapse, the linear regions are very wide and the intervals between graphs are uniform as in Figure 11(b). The linearity of the memristor bridge synaptic circuit comes from the linear weight assignment at the memristor bridge synapse and the operation at the middle of the memristor dynamic range.

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.