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A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.


Weight variations of the memristor bridge circuit while positive and negative pulses are applied (a) positive and negative input pulses; (b) weight variations during each pulse period.
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f10-sensors-12-03587: Weight variations of the memristor bridge circuit while positive and negative pulses are applied (a) positive and negative input pulses; (b) weight variations during each pulse period.

Mentions: The linearity of the weight programming of the memristor emulator-based memristor bridge synapse has been tested by applying wide positive and negative pulses. The weight values were computed by measuring the output voltages of the memristor bridge circuit while known input voltages were applied, as described in Section 4.1 and 4.2. The results of circuit simulations for the synaptic weighting are shown in Figure 10.


A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Weight variations of the memristor bridge circuit while positive and negative pulses are applied (a) positive and negative input pulses; (b) weight variations during each pulse period.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376599&req=5

f10-sensors-12-03587: Weight variations of the memristor bridge circuit while positive and negative pulses are applied (a) positive and negative input pulses; (b) weight variations during each pulse period.
Mentions: The linearity of the weight programming of the memristor emulator-based memristor bridge synapse has been tested by applying wide positive and negative pulses. The weight values were computed by measuring the output voltages of the memristor bridge circuit while known input voltages were applied, as described in Section 4.1 and 4.2. The results of circuit simulations for the synaptic weighting are shown in Figure 10.

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.