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Using SRAM based FPGAs for power-aware high performance wireless sensor networks.

Valverde J, Otero A, Lopez M, Portilla J, de la Torre E, Riesgo T - Sensors (Basel) (2012)

Bottom Line: At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall.This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved.Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

View Article: PubMed Central - PubMed

Affiliation: Centro de Electronica Industrial, Universidad Politecnica de Madrid, Madrid 28006, Spain. juan.valverde@upm.es

ABSTRACT
While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today's applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

No MeSH data available.


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Mentions: The power consumption profile of the FPGA core is shown in Figure 8. On this oscilloscope image, the system is awakened every 5 s to encrypt 128 data blocks using the SHA1 algorithm. The time interval labeled 1 show the sleeping time of the node. The second period corresponds to power consumption during configuration, while the power consumption peak represents the actual FPGA activity. Numerical results are detailed in Table 3. Even though the current peak is quite high, the power supply board uses an integrated DC to DC converter from Texas Instruments (TPS650243) which is capable of giving up to 1.6 A. Nevertheless, for these tests, as it was mentioned before, an expansion board and external power supplies have been used. The wave form labeled as D10 shows the triggers to measure the computing and configuration times.


Using SRAM based FPGAs for power-aware high performance wireless sensor networks.

Valverde J, Otero A, Lopez M, Portilla J, de la Torre E, Riesgo T - Sensors (Basel) (2012)

Test 1 SHA1.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376580&req=5

f8-sensors-12-02667: Test 1 SHA1.
Mentions: The power consumption profile of the FPGA core is shown in Figure 8. On this oscilloscope image, the system is awakened every 5 s to encrypt 128 data blocks using the SHA1 algorithm. The time interval labeled 1 show the sleeping time of the node. The second period corresponds to power consumption during configuration, while the power consumption peak represents the actual FPGA activity. Numerical results are detailed in Table 3. Even though the current peak is quite high, the power supply board uses an integrated DC to DC converter from Texas Instruments (TPS650243) which is capable of giving up to 1.6 A. Nevertheless, for these tests, as it was mentioned before, an expansion board and external power supplies have been used. The wave form labeled as D10 shows the triggers to measure the computing and configuration times.

Bottom Line: At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall.This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved.Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

View Article: PubMed Central - PubMed

Affiliation: Centro de Electronica Industrial, Universidad Politecnica de Madrid, Madrid 28006, Spain. juan.valverde@upm.es

ABSTRACT
While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today's applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

No MeSH data available.