Limits...
CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Ding L, Zhang Z, Liang S, Pei T, Wang S, Li Y, Zhou W, Liu J, Peng LM - Nat Commun (2012)

Bottom Line: Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration.The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption.In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

View Article: PubMed Central - PubMed

Affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices, and Department of Electronics, Peking University, Beijing 100871, China.

ABSTRACT
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Show MeSH
CMOS and PTL hybrid circuits.(a) Circuit design for an XOR gate with a cascading CMOS inverter. (b) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a cascading CMOS inverter. (c) Circuit design for an XOR gate with a driving CMOS inverter. (d) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a CMOS inverter as its driving circuit.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
getmorefigures.php?uid=PMC3293427&req=5

f5: CMOS and PTL hybrid circuits.(a) Circuit design for an XOR gate with a cascading CMOS inverter. (b) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a cascading CMOS inverter. (c) Circuit design for an XOR gate with a driving CMOS inverter. (d) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a CMOS inverter as its driving circuit.

Mentions: The degraded output in multi-stage circuits can be restored to its ideal value by simply cascading a CMOS inverter with a gain larger than 1. As shown in Fig. 5a, when connecting a CMOS inverter to the output of a PTL XOR gate (or a semi-adder), the degraded output high level (at approximately 0.67 V) for the input combination (A, B)=(0, 1) from the XOR gate is converted to an almost ideal low level (approximately 0.02 V, Fig. 5b). Alternatively, the CMOS inverter can also be used to drive a PTL circuit such as the XOR gate, providing a performance similar to that using an ideal voltage source (Fig. 5c and d). Therefore, a CMOS inverter with a voltage gain much larger than 1 can be used in combination with PTL circuits to provide signal gain and restore the degraded signal, and to drive the next stage of the PTL gate, that is, the CNT-based PTL circuits can be used in combination with CMOS circuits to provide more reliable and complicated logic ICs without introducing any additional fabrication process.


CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Ding L, Zhang Z, Liang S, Pei T, Wang S, Li Y, Zhou W, Liu J, Peng LM - Nat Commun (2012)

CMOS and PTL hybrid circuits.(a) Circuit design for an XOR gate with a cascading CMOS inverter. (b) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a cascading CMOS inverter. (c) Circuit design for an XOR gate with a driving CMOS inverter. (d) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a CMOS inverter as its driving circuit.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3293427&req=5

f5: CMOS and PTL hybrid circuits.(a) Circuit design for an XOR gate with a cascading CMOS inverter. (b) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a cascading CMOS inverter. (c) Circuit design for an XOR gate with a driving CMOS inverter. (d) Output voltage levels for all four input states of the XOR gate without (blue spheres) and with (green spheres) a CMOS inverter as its driving circuit.
Mentions: The degraded output in multi-stage circuits can be restored to its ideal value by simply cascading a CMOS inverter with a gain larger than 1. As shown in Fig. 5a, when connecting a CMOS inverter to the output of a PTL XOR gate (or a semi-adder), the degraded output high level (at approximately 0.67 V) for the input combination (A, B)=(0, 1) from the XOR gate is converted to an almost ideal low level (approximately 0.02 V, Fig. 5b). Alternatively, the CMOS inverter can also be used to drive a PTL circuit such as the XOR gate, providing a performance similar to that using an ideal voltage source (Fig. 5c and d). Therefore, a CMOS inverter with a voltage gain much larger than 1 can be used in combination with PTL circuits to provide signal gain and restore the degraded signal, and to drive the next stage of the PTL gate, that is, the CNT-based PTL circuits can be used in combination with CMOS circuits to provide more reliable and complicated logic ICs without introducing any additional fabrication process.

Bottom Line: Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration.The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption.In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

View Article: PubMed Central - PubMed

Affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices, and Department of Electronics, Peking University, Beijing 100871, China.

ABSTRACT
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Show MeSH