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CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Ding L, Zhang Z, Liang S, Pei T, Wang S, Li Y, Zhou W, Liu J, Peng LM - Nat Commun (2012)

Bottom Line: Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration.The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption.In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

View Article: PubMed Central - PubMed

Affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices, and Department of Electronics, Peking University, Beijing 100871, China.

ABSTRACT
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

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CMOS-based pass-transistor OR and AND gates.(a) Circuit design (top) and truth table (bottom) for an OR gate. (b) Output voltage levels for all four input states of the OR gate. (c) Circuit design (top) and truth table (bottom) for an AND gate. (d) Output voltage levels for all four input states of the AND gate.
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f3: CMOS-based pass-transistor OR and AND gates.(a) Circuit design (top) and truth table (bottom) for an OR gate. (b) Output voltage levels for all four input states of the OR gate. (c) Circuit design (top) and truth table (bottom) for an AND gate. (d) Output voltage levels for all four input states of the AND gate.

Mentions: We first consider the OR gate. Figure 3a is a circuit diagram designed with a PTL configuration together with a truth table for the OR gate. The outputs for all four (A, B) input combinations are shown in Fig. 3b, illustrating an excellent OR logic function. Among the four outputs, those corresponding to the input combinations (A, B)=(0, 0) and (1, 1) are almost perfect, whereas the outputs for the input combinations (A, B)=(0, 1) and (1, 0) are 0.96 V and 0.97 V, respectively, for a power supply of VDD=1 V, and are thus slightly degraded. The output voltage drop for each input combination depends mainly on the threshold voltages of the involved CNT FETs and can be estimated from the output characteristics of the device.


CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Ding L, Zhang Z, Liang S, Pei T, Wang S, Li Y, Zhou W, Liu J, Peng LM - Nat Commun (2012)

CMOS-based pass-transistor OR and AND gates.(a) Circuit design (top) and truth table (bottom) for an OR gate. (b) Output voltage levels for all four input states of the OR gate. (c) Circuit design (top) and truth table (bottom) for an AND gate. (d) Output voltage levels for all four input states of the AND gate.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3293427&req=5

f3: CMOS-based pass-transistor OR and AND gates.(a) Circuit design (top) and truth table (bottom) for an OR gate. (b) Output voltage levels for all four input states of the OR gate. (c) Circuit design (top) and truth table (bottom) for an AND gate. (d) Output voltage levels for all four input states of the AND gate.
Mentions: We first consider the OR gate. Figure 3a is a circuit diagram designed with a PTL configuration together with a truth table for the OR gate. The outputs for all four (A, B) input combinations are shown in Fig. 3b, illustrating an excellent OR logic function. Among the four outputs, those corresponding to the input combinations (A, B)=(0, 0) and (1, 1) are almost perfect, whereas the outputs for the input combinations (A, B)=(0, 1) and (1, 0) are 0.96 V and 0.97 V, respectively, for a power supply of VDD=1 V, and are thus slightly degraded. The output voltage drop for each input combination depends mainly on the threshold voltages of the involved CNT FETs and can be estimated from the output characteristics of the device.

Bottom Line: Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration.The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption.In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

View Article: PubMed Central - PubMed

Affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices, and Department of Electronics, Peking University, Beijing 100871, China.

ABSTRACT
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Show MeSH