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Thermal conductivity and thermal boundary resistance of nanostructures.

Termentzidis K, Parasuraman J, Da Cruz CA, Merabia S, Angelescu D, Marty F, Bourouina T, Kleber X, Chantrenne P, Basset P - Nanoscale Res Lett (2011)

Bottom Line: The influence of the interfacial roughness on the thermal conductivity of semiconductor/semiconductor superlattices was studied by equilibrium and non-equilibrium molecular dynamics and on the Kapitza resistance of superlattice's interfaces by equilibrium molecular dynamics.Physical explanations are provided for rationalizing the simulation results.PACS: 68.65.Cd, 66.70.Df, 81.16.-c, 65.80.-g, 31.12.xv.

View Article: PubMed Central - HTML - PubMed

Affiliation: INSA Lyon, CETHIL UMR5008, F-69621 Villeurbanne, France. konstantinos.termentzidis@gmail.com.

ABSTRACT
: We present a fabrication process of low-cost superlattices and simulations related with the heat dissipation on them. The influence of the interfacial roughness on the thermal conductivity of semiconductor/semiconductor superlattices was studied by equilibrium and non-equilibrium molecular dynamics and on the Kapitza resistance of superlattice's interfaces by equilibrium molecular dynamics. The non-equilibrium method was the tool used for the prediction of the Kapitza resistance for a binary semiconductor/metal system. Physical explanations are provided for rationalizing the simulation results. PACS: 68.65.Cd, 66.70.Df, 81.16.-c, 65.80.-g, 31.12.xv.

No MeSH data available.


Related in: MedlinePlus

SEM image of copper-filled 5-μm-wide trenches.
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Figure 3: SEM image of copper-filled 5-μm-wide trenches.

Mentions: Vertical superlattices were obtained by patterning and then etching the silicon by deep reactive ion etching (DRIE). The trenches were filled using electrodeposition on a thin metallic seed layer. In Figure 3, a scanning electron microscope (SEM) image of a processed silicon wafer with micro-superlattices is given. There are voids at the bottom of the trenches which are explained by the absence of the seed layer at the bottom, and the fact that they prevent any copper growth. These voids were successfully eliminated by increasing the amount of seed layer sputtered in subsequent trials. The excess copper on top, resulting from the trenches being shorted to facilitate electroplating, was polished away using chemical-mechanical polishing. This is done to electrically isolate the trenches from one another so as to allow thermo-electrical conversion.


Thermal conductivity and thermal boundary resistance of nanostructures.

Termentzidis K, Parasuraman J, Da Cruz CA, Merabia S, Angelescu D, Marty F, Bourouina T, Kleber X, Chantrenne P, Basset P - Nanoscale Res Lett (2011)

SEM image of copper-filled 5-μm-wide trenches.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3211353&req=5

Figure 3: SEM image of copper-filled 5-μm-wide trenches.
Mentions: Vertical superlattices were obtained by patterning and then etching the silicon by deep reactive ion etching (DRIE). The trenches were filled using electrodeposition on a thin metallic seed layer. In Figure 3, a scanning electron microscope (SEM) image of a processed silicon wafer with micro-superlattices is given. There are voids at the bottom of the trenches which are explained by the absence of the seed layer at the bottom, and the fact that they prevent any copper growth. These voids were successfully eliminated by increasing the amount of seed layer sputtered in subsequent trials. The excess copper on top, resulting from the trenches being shorted to facilitate electroplating, was polished away using chemical-mechanical polishing. This is done to electrically isolate the trenches from one another so as to allow thermo-electrical conversion.

Bottom Line: The influence of the interfacial roughness on the thermal conductivity of semiconductor/semiconductor superlattices was studied by equilibrium and non-equilibrium molecular dynamics and on the Kapitza resistance of superlattice's interfaces by equilibrium molecular dynamics.Physical explanations are provided for rationalizing the simulation results.PACS: 68.65.Cd, 66.70.Df, 81.16.-c, 65.80.-g, 31.12.xv.

View Article: PubMed Central - HTML - PubMed

Affiliation: INSA Lyon, CETHIL UMR5008, F-69621 Villeurbanne, France. konstantinos.termentzidis@gmail.com.

ABSTRACT
: We present a fabrication process of low-cost superlattices and simulations related with the heat dissipation on them. The influence of the interfacial roughness on the thermal conductivity of semiconductor/semiconductor superlattices was studied by equilibrium and non-equilibrium molecular dynamics and on the Kapitza resistance of superlattice's interfaces by equilibrium molecular dynamics. The non-equilibrium method was the tool used for the prediction of the Kapitza resistance for a binary semiconductor/metal system. Physical explanations are provided for rationalizing the simulation results. PACS: 68.65.Cd, 66.70.Df, 81.16.-c, 65.80.-g, 31.12.xv.

No MeSH data available.


Related in: MedlinePlus