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Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films.

Sahu BS, Delachat F, Slaoui A, Carrada M, Ferblantier G, Muller D - Nanoscale Res Lett (2011)

Bottom Line: The silicon-rich a-SiNx:H films (SRSN) were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 to study the effect of annealing temperature on light-emitting and charge storage properties.A strong visible photoluminescence (PL) at room temperature has been observed for the as-deposited SRSN films as well as for films annealed up to 1100°C.A significant memory window of 4.45 V was obtained at a low operating voltage of ± 8 V for the sample containing 25% excess silicon and annealed at 1000°C, indicating its utility in low-power memory devices.

View Article: PubMed Central - HTML - PubMed

Affiliation: InESS-UdS-CNRS, 23 Rue du Loess, 67037 Strasbourg, France. sahu.bhabani@iness.c-strasbourg.fr.

ABSTRACT
In this study, a wide range of a-SiNx:H films with an excess of silicon (20 to 50%) were prepared with an electron-cyclotron resonance plasma-enhanced chemical vapor deposition system under the flows of NH3 and SiH4. The silicon-rich a-SiNx:H films (SRSN) were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 to study the effect of annealing temperature on light-emitting and charge storage properties. A strong visible photoluminescence (PL) at room temperature has been observed for the as-deposited SRSN films as well as for films annealed up to 1100°C. The possible origins of the PL are briefly discussed. The authors have succeeded in the formation of amorphous Si quantum dots with an average size of about 3 to 3.6 nm by varying excess amount of Si and annealing temperature. Electrical properties have been investigated on Al/Si3N4/SRSN/SiO2/Si structures by capacitance-voltage and conductance-voltage analysis techniques. A significant memory window of 4.45 V was obtained at a low operating voltage of ± 8 V for the sample containing 25% excess silicon and annealed at 1000°C, indicating its utility in low-power memory devices.

No MeSH data available.


(Color online) High-frequency (100 kHz) C-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) memory capacitors of (a) the sample S4 containing 33 at.% of excess silicon, (b) the sample S2 containing 25 at.% of excess silicon, (c) evolution of memory window (calculated from flat-band shifts) versus excess silicon at two different annealing temperatures (1000 and 1100°C).
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Figure 6: (Color online) High-frequency (100 kHz) C-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) memory capacitors of (a) the sample S4 containing 33 at.% of excess silicon, (b) the sample S2 containing 25 at.% of excess silicon, (c) evolution of memory window (calculated from flat-band shifts) versus excess silicon at two different annealing temperatures (1000 and 1100°C).

Mentions: Figure 6a,b shows the typical high-frequency (100 kHz) C-V curves of Al/Si3N4/SRSN/SiO2/Si (MNNOS) capacitors with different excess amount of Si (33 and 25 at.%), and subjected to a post-thermal annealing at 1100°C in N2 ambient. All the capacitors show well-defined accumulation, depletion, and inversion regions in the C-V curves. Except S4 (33 at.% of excess Si), all other capacitors exhibit a sharp transition from accumulation and depletion to inversion, indicating the presence of less number of interface traps in the samples. In contrast, small irregularities or smear-out effect have been observed in the depletion region capacitance of sample S4, indicating the presence of some border (near-interfacial) traps in the MNNOS capacitor. All the capacitors show clockwise hysteresis, indicating a net positive charge (hole) trapping in the MNNOS capacitors [43]. The clockwise nature of C-V curves is generally attributed to charge storage through gate-injection mechanism. In fact, owing to rather thicker SiO2 interfacial layer, the substrate injection of carriers has been suppressed, which otherwise gives counterclockwise hysteresis loop. Under the influence of a positive bias voltage, holes are injected into the SRSN film from the top Al gate electrode, creating an abundance of holes in the SRSN charge-trapping layer. This promotes the injection of holes from the SRSN layer to the citrated Si-nps and/or defects inside the SRSN matrix, leading to a net hole trapping. Upon applying a negative bias voltage, the holes are subsequently flushed out (equivalent to injection of electrons) from the SRSN charge-trapping layer to the gate electrode, resulting in a negative flatband voltage shift and clockwise hysteresis loop. In addition, the presence of mobile ions and/or dielectric polarization can always give rise to a clockwise hysteresis. However, such a large amount of hysteresis window obtained at room temperature cannot be attributed to mobile charges, as their contribution is negligible at room temperature. In addition, the presence of mobile ions in the dielectric films leads to clockwise hysteresis, but no flatband shift in the positive sweep direction. This is inconsistent with the above results of C-V hysteresis, where a huge positive shift of flatband voltage has been noticed. Thus, the observed memory window can be safely assigned to charge storage in Si-nps and/or deep traps inside SRSN matrix. Contrary to what was expected, the sample S4 with the highest content of Si excess exhibits the lowest hysteretic effect, even though EFTEM images clearly indicate the existence of Si-nps. It is speculated that the reduced memory window is due to lateral charge loss through leakage paths introduced by insufficiently localized Si-nps and defect sites. It has been observed that the sample S2 with 25 at.% of Si excess exhibits the highest hysteretic effect, even though no Si-np was detected in our EFTEM analysis. An estimated memory window of 4.45 V was obtained at a sweep voltage of ± 8 V. The memory effect in the absence of Si-nps can be attributed to charge storage in deep level traps in the SRSN matrix and/or excess of Si at SRSN/SiO2 interface. Such type of charge storage has been obtained for SONOS-type memory structure having a SRSN charge-trapping layer [44,45]. Different models of electron and hole traps have been proposed for silicon nitride films. First, the model of dangling Si bonds as a capturing center [46,47]. Second, the presence of three fold coordinated negatively (K- center) and positively (K+ center) charged silicon atoms as traps for holes and electrons, respectively [48], and third to Si-Si bond or nitrogen vacancy possibly being responsible for electron and hole localization [49]. According to Robertson and Powell [36], SRSN films subjected to high-temperature annealing contain a significant amount of ≡ Si° defects, which behave as memory trap because it is amphoteric, deep, and energetically aligned with the gap of Si. These traps can trap either electrons or holes during programming, and release them during erase process. However, the trapping phenomena in silicon nitride are rather complicated and detailed investigation is in progress. As evident from Figure 6a,b, the conductance peak position in the samples are situated close to the flat-band voltage of the C-V curves. The separation of the conductance peak position during bidirectional sweep agrees well with the memory window values obtained from C-V measurements. Except the sample S4, all other samples exhibit single conductance peak in both forward and reverse sweep directions, indicating single electron charging effect. However, the sample S4 exhibits two peaks in bidirectional sweep, indicating sequential trapping and detrapping of two electrons [50]. The difference in peak heights during forward and reverse sweep can be attributed to different charge states of the traps in both sweep directions. Thus, we can conclude that the charge storage properties of SRSN layers can be enhanced by suitably tuning the Si excess content and annealing conditions. Figure 6c exhibits the variation of memory window for all the samples at two different annealing temperatures of 1000 and 1100°C. In our study, 1000°C was found to be the optimum annealing temperature for getting larger charge storage capacity in the MNNOS memory capacitors.


Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films.

Sahu BS, Delachat F, Slaoui A, Carrada M, Ferblantier G, Muller D - Nanoscale Res Lett (2011)

(Color online) High-frequency (100 kHz) C-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) memory capacitors of (a) the sample S4 containing 33 at.% of excess silicon, (b) the sample S2 containing 25 at.% of excess silicon, (c) evolution of memory window (calculated from flat-band shifts) versus excess silicon at two different annealing temperatures (1000 and 1100°C).
© Copyright Policy - open-access
Related In: Results  -  Collection

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Show All Figures
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Figure 6: (Color online) High-frequency (100 kHz) C-V characteristics of Al/Si3N4/SRSN/SiO2/Si (MNNOS) memory capacitors of (a) the sample S4 containing 33 at.% of excess silicon, (b) the sample S2 containing 25 at.% of excess silicon, (c) evolution of memory window (calculated from flat-band shifts) versus excess silicon at two different annealing temperatures (1000 and 1100°C).
Mentions: Figure 6a,b shows the typical high-frequency (100 kHz) C-V curves of Al/Si3N4/SRSN/SiO2/Si (MNNOS) capacitors with different excess amount of Si (33 and 25 at.%), and subjected to a post-thermal annealing at 1100°C in N2 ambient. All the capacitors show well-defined accumulation, depletion, and inversion regions in the C-V curves. Except S4 (33 at.% of excess Si), all other capacitors exhibit a sharp transition from accumulation and depletion to inversion, indicating the presence of less number of interface traps in the samples. In contrast, small irregularities or smear-out effect have been observed in the depletion region capacitance of sample S4, indicating the presence of some border (near-interfacial) traps in the MNNOS capacitor. All the capacitors show clockwise hysteresis, indicating a net positive charge (hole) trapping in the MNNOS capacitors [43]. The clockwise nature of C-V curves is generally attributed to charge storage through gate-injection mechanism. In fact, owing to rather thicker SiO2 interfacial layer, the substrate injection of carriers has been suppressed, which otherwise gives counterclockwise hysteresis loop. Under the influence of a positive bias voltage, holes are injected into the SRSN film from the top Al gate electrode, creating an abundance of holes in the SRSN charge-trapping layer. This promotes the injection of holes from the SRSN layer to the citrated Si-nps and/or defects inside the SRSN matrix, leading to a net hole trapping. Upon applying a negative bias voltage, the holes are subsequently flushed out (equivalent to injection of electrons) from the SRSN charge-trapping layer to the gate electrode, resulting in a negative flatband voltage shift and clockwise hysteresis loop. In addition, the presence of mobile ions and/or dielectric polarization can always give rise to a clockwise hysteresis. However, such a large amount of hysteresis window obtained at room temperature cannot be attributed to mobile charges, as their contribution is negligible at room temperature. In addition, the presence of mobile ions in the dielectric films leads to clockwise hysteresis, but no flatband shift in the positive sweep direction. This is inconsistent with the above results of C-V hysteresis, where a huge positive shift of flatband voltage has been noticed. Thus, the observed memory window can be safely assigned to charge storage in Si-nps and/or deep traps inside SRSN matrix. Contrary to what was expected, the sample S4 with the highest content of Si excess exhibits the lowest hysteretic effect, even though EFTEM images clearly indicate the existence of Si-nps. It is speculated that the reduced memory window is due to lateral charge loss through leakage paths introduced by insufficiently localized Si-nps and defect sites. It has been observed that the sample S2 with 25 at.% of Si excess exhibits the highest hysteretic effect, even though no Si-np was detected in our EFTEM analysis. An estimated memory window of 4.45 V was obtained at a sweep voltage of ± 8 V. The memory effect in the absence of Si-nps can be attributed to charge storage in deep level traps in the SRSN matrix and/or excess of Si at SRSN/SiO2 interface. Such type of charge storage has been obtained for SONOS-type memory structure having a SRSN charge-trapping layer [44,45]. Different models of electron and hole traps have been proposed for silicon nitride films. First, the model of dangling Si bonds as a capturing center [46,47]. Second, the presence of three fold coordinated negatively (K- center) and positively (K+ center) charged silicon atoms as traps for holes and electrons, respectively [48], and third to Si-Si bond or nitrogen vacancy possibly being responsible for electron and hole localization [49]. According to Robertson and Powell [36], SRSN films subjected to high-temperature annealing contain a significant amount of ≡ Si° defects, which behave as memory trap because it is amphoteric, deep, and energetically aligned with the gap of Si. These traps can trap either electrons or holes during programming, and release them during erase process. However, the trapping phenomena in silicon nitride are rather complicated and detailed investigation is in progress. As evident from Figure 6a,b, the conductance peak position in the samples are situated close to the flat-band voltage of the C-V curves. The separation of the conductance peak position during bidirectional sweep agrees well with the memory window values obtained from C-V measurements. Except the sample S4, all other samples exhibit single conductance peak in both forward and reverse sweep directions, indicating single electron charging effect. However, the sample S4 exhibits two peaks in bidirectional sweep, indicating sequential trapping and detrapping of two electrons [50]. The difference in peak heights during forward and reverse sweep can be attributed to different charge states of the traps in both sweep directions. Thus, we can conclude that the charge storage properties of SRSN layers can be enhanced by suitably tuning the Si excess content and annealing conditions. Figure 6c exhibits the variation of memory window for all the samples at two different annealing temperatures of 1000 and 1100°C. In our study, 1000°C was found to be the optimum annealing temperature for getting larger charge storage capacity in the MNNOS memory capacitors.

Bottom Line: The silicon-rich a-SiNx:H films (SRSN) were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 to study the effect of annealing temperature on light-emitting and charge storage properties.A strong visible photoluminescence (PL) at room temperature has been observed for the as-deposited SRSN films as well as for films annealed up to 1100°C.A significant memory window of 4.45 V was obtained at a low operating voltage of ± 8 V for the sample containing 25% excess silicon and annealed at 1000°C, indicating its utility in low-power memory devices.

View Article: PubMed Central - HTML - PubMed

Affiliation: InESS-UdS-CNRS, 23 Rue du Loess, 67037 Strasbourg, France. sahu.bhabani@iness.c-strasbourg.fr.

ABSTRACT
In this study, a wide range of a-SiNx:H films with an excess of silicon (20 to 50%) were prepared with an electron-cyclotron resonance plasma-enhanced chemical vapor deposition system under the flows of NH3 and SiH4. The silicon-rich a-SiNx:H films (SRSN) were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 to study the effect of annealing temperature on light-emitting and charge storage properties. A strong visible photoluminescence (PL) at room temperature has been observed for the as-deposited SRSN films as well as for films annealed up to 1100°C. The possible origins of the PL are briefly discussed. The authors have succeeded in the formation of amorphous Si quantum dots with an average size of about 3 to 3.6 nm by varying excess amount of Si and annealing temperature. Electrical properties have been investigated on Al/Si3N4/SRSN/SiO2/Si structures by capacitance-voltage and conductance-voltage analysis techniques. A significant memory window of 4.45 V was obtained at a low operating voltage of ± 8 V for the sample containing 25% excess silicon and annealed at 1000°C, indicating its utility in low-power memory devices.

No MeSH data available.