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Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


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C-V characteristics of annealed HfO2/SRSO/SiO2. C-V characteristics of HfO2/SRSO/SiO2 annealed at 800°C for 15 min (a, b) and at 950°C for 15 min (c, d) measured at 1 MHz (a, c) and versus frequency measured at 6 V sweep voltage (b, d). (e) The variation of ΔVfb versus sweep voltage for two annealing temperatures; (f) the comparison of C-V curves measured at 1 MHz versus annealing temperature. Annealing time is 15 min for all the figures.
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Figure 4: C-V characteristics of annealed HfO2/SRSO/SiO2. C-V characteristics of HfO2/SRSO/SiO2 annealed at 800°C for 15 min (a, b) and at 950°C for 15 min (c, d) measured at 1 MHz (a, c) and versus frequency measured at 6 V sweep voltage (b, d). (e) The variation of ΔVfb versus sweep voltage for two annealing temperatures; (f) the comparison of C-V curves measured at 1 MHz versus annealing temperature. Annealing time is 15 min for all the figures.

Mentions: Figure 4a shows the C-V curves of HfO2/SRSO/SiO2 stack structures annealed at 800°C for 15 min in the MIS structure taken at various sweep voltages. The hysteresis memory window increases from approximately 1 V to approximately 6 V with increasing the sweep voltage from ± 4 to ± 10 V. The counterclockwise nature of the hysteresis loop indicates net electron trapping in the MIS capacitor. However, frequency-dependent C-V curves show nonparallel shifts with varying measurement frequency, indicating the presence of some interfacial traps and/or border tarps in the MIS capacitor. We speculate that the charge trapping is due to near interfacial traps and excess of silicon at SRSO/SiO2 and SRSO/HfO2 interfaces rather than Si-ncs.


Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

C-V characteristics of annealed HfO2/SRSO/SiO2. C-V characteristics of HfO2/SRSO/SiO2 annealed at 800°C for 15 min (a, b) and at 950°C for 15 min (c, d) measured at 1 MHz (a, c) and versus frequency measured at 6 V sweep voltage (b, d). (e) The variation of ΔVfb versus sweep voltage for two annealing temperatures; (f) the comparison of C-V curves measured at 1 MHz versus annealing temperature. Annealing time is 15 min for all the figures.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3211225&req=5

Figure 4: C-V characteristics of annealed HfO2/SRSO/SiO2. C-V characteristics of HfO2/SRSO/SiO2 annealed at 800°C for 15 min (a, b) and at 950°C for 15 min (c, d) measured at 1 MHz (a, c) and versus frequency measured at 6 V sweep voltage (b, d). (e) The variation of ΔVfb versus sweep voltage for two annealing temperatures; (f) the comparison of C-V curves measured at 1 MHz versus annealing temperature. Annealing time is 15 min for all the figures.
Mentions: Figure 4a shows the C-V curves of HfO2/SRSO/SiO2 stack structures annealed at 800°C for 15 min in the MIS structure taken at various sweep voltages. The hysteresis memory window increases from approximately 1 V to approximately 6 V with increasing the sweep voltage from ± 4 to ± 10 V. The counterclockwise nature of the hysteresis loop indicates net electron trapping in the MIS capacitor. However, frequency-dependent C-V curves show nonparallel shifts with varying measurement frequency, indicating the presence of some interfacial traps and/or border tarps in the MIS capacitor. We speculate that the charge trapping is due to near interfacial traps and excess of silicon at SRSO/SiO2 and SRSO/HfO2 interfaces rather than Si-ncs.

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


Related in: MedlinePlus