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Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


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C-V data of single HfSiO layer and HfSiO/SRSO/HfSiO structure measured at different frequencies. Comparison of C-V data for single HfSiO layer (a) and HfSiO/SRSO/HfSiO structure (b) measured at different frequencies. RSi = 12%. Annealing treatment at TA = 950°C, tA = 15 min, N2 flow. Inset of figure (b) demonstrates variation of ΔVfb versus applied frequency at 6 V sweep voltage.
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Figure 3: C-V data of single HfSiO layer and HfSiO/SRSO/HfSiO structure measured at different frequencies. Comparison of C-V data for single HfSiO layer (a) and HfSiO/SRSO/HfSiO structure (b) measured at different frequencies. RSi = 12%. Annealing treatment at TA = 950°C, tA = 15 min, N2 flow. Inset of figure (b) demonstrates variation of ΔVfb versus applied frequency at 6 V sweep voltage.

Mentions: First of all, let us consider electrical properties of HfSiO/SRSO/HfSiO (or SiO2) structures. As it was mentioned above, these structures can be fabricated at higher temperatures since HfSiO layers conserve their amorphous structure at TS = 400°C to 500°C and TA = 950°C. Thus, the annealing was performed at TA = 800°C to 1,100°C for TA = 15 min in nitrogen flow to obtain the information about memory effect caused by Si-ncs. As one can see from the Figure 3a, C-V curves of Al/HfSiO/Si capacitor structures show a sharp transition from accumulation to inversion, indicating a low density of interface states in the samples under study. The MIS structures show negligible hysteresis loop. In contrast, Al/HfSiO/SRSO/HfSiO/p-Si memory structures exhibit significant counterclockwise hysteresis loop, and the memory window (ΔVfb) was estimated to be approximately 1.7 V from flat-band voltage values. The counterclockwise nature of C-V curves is generally attributed to charge storage through substrate injection mechanism. When a positive bias voltage is applied, electrons are being injected from the inversion layer of the Si substrate into the gate dielectric matrix. When a negative voltage is applied, electrons are ejected back into the Si substrate (equivalent to hole injection from the deep accumulation layer of the substrate), resulting in a shift of the C-V curve towards negative voltages. It is interesting to note that the C-V curves of Al/HfSiO/SRSO/HfSiO/p-Si memory structures shift towards more positive bias with decreasing frequency, and the shift is more prominent in the low frequency region. The shift is marked by minimal frequency dispersion in accumulation, capacitance indicating minimal influence of series resistance, and dielectric constant variation with altering the measurement frequency. From the inset of Figure 3b, it is noteworthy that the same amount of hysteresis and stored charge was obtained irrespective of the measurement frequency. Hence, the capacitance shift can be attributed to the presence of fast traps and/or border traps (near-interfacial traps), which can have a rapid communication with the underlying Si substrate [24]. From all these observations, we can ascertain that the observed memory window is predominantly due to the formation of Si-ncs. It should be noted that an annealing at 950°C for 15 min was found to provide the highest ΔVfb value, whereas the increase or decrease of TA results in the essential decrease of ΔVfb. For lower annealing temperatures, this effect can be due to noncompleted phase separation within the SRSO layer. For higher annealing temperatures, complete oxidation of SRSO layer should occur. Besides, the phase separation inside HfSiO layers can occur as it was demonstrated in [25].


Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

C-V data of single HfSiO layer and HfSiO/SRSO/HfSiO structure measured at different frequencies. Comparison of C-V data for single HfSiO layer (a) and HfSiO/SRSO/HfSiO structure (b) measured at different frequencies. RSi = 12%. Annealing treatment at TA = 950°C, tA = 15 min, N2 flow. Inset of figure (b) demonstrates variation of ΔVfb versus applied frequency at 6 V sweep voltage.
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Figure 3: C-V data of single HfSiO layer and HfSiO/SRSO/HfSiO structure measured at different frequencies. Comparison of C-V data for single HfSiO layer (a) and HfSiO/SRSO/HfSiO structure (b) measured at different frequencies. RSi = 12%. Annealing treatment at TA = 950°C, tA = 15 min, N2 flow. Inset of figure (b) demonstrates variation of ΔVfb versus applied frequency at 6 V sweep voltage.
Mentions: First of all, let us consider electrical properties of HfSiO/SRSO/HfSiO (or SiO2) structures. As it was mentioned above, these structures can be fabricated at higher temperatures since HfSiO layers conserve their amorphous structure at TS = 400°C to 500°C and TA = 950°C. Thus, the annealing was performed at TA = 800°C to 1,100°C for TA = 15 min in nitrogen flow to obtain the information about memory effect caused by Si-ncs. As one can see from the Figure 3a, C-V curves of Al/HfSiO/Si capacitor structures show a sharp transition from accumulation to inversion, indicating a low density of interface states in the samples under study. The MIS structures show negligible hysteresis loop. In contrast, Al/HfSiO/SRSO/HfSiO/p-Si memory structures exhibit significant counterclockwise hysteresis loop, and the memory window (ΔVfb) was estimated to be approximately 1.7 V from flat-band voltage values. The counterclockwise nature of C-V curves is generally attributed to charge storage through substrate injection mechanism. When a positive bias voltage is applied, electrons are being injected from the inversion layer of the Si substrate into the gate dielectric matrix. When a negative voltage is applied, electrons are ejected back into the Si substrate (equivalent to hole injection from the deep accumulation layer of the substrate), resulting in a shift of the C-V curve towards negative voltages. It is interesting to note that the C-V curves of Al/HfSiO/SRSO/HfSiO/p-Si memory structures shift towards more positive bias with decreasing frequency, and the shift is more prominent in the low frequency region. The shift is marked by minimal frequency dispersion in accumulation, capacitance indicating minimal influence of series resistance, and dielectric constant variation with altering the measurement frequency. From the inset of Figure 3b, it is noteworthy that the same amount of hysteresis and stored charge was obtained irrespective of the measurement frequency. Hence, the capacitance shift can be attributed to the presence of fast traps and/or border traps (near-interfacial traps), which can have a rapid communication with the underlying Si substrate [24]. From all these observations, we can ascertain that the observed memory window is predominantly due to the formation of Si-ncs. It should be noted that an annealing at 950°C for 15 min was found to provide the highest ΔVfb value, whereas the increase or decrease of TA results in the essential decrease of ΔVfb. For lower annealing temperatures, this effect can be due to noncompleted phase separation within the SRSO layer. For higher annealing temperatures, complete oxidation of SRSO layer should occur. Besides, the phase separation inside HfSiO layers can occur as it was demonstrated in [25].

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


Related in: MedlinePlus