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Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


Related in: MedlinePlus

XRD patterns and PL spectra of SRSO/SiO2 multilayers. (a) GI-XRD patterns measured for [2-nm-SRSO/SiO2]20 and [3-nm-SRSO/SiO2]20 multistacks annealed at 1,100°C for 60 min. Inset, PL spectra of the same MLs. The thickness of SRSO layer for each ML is mentioned in the figure. (b) PL properties of the [2-nm-SRSO/SiO2]20 ML versus annealing temperature; annealing time is 15 min.
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Figure 2: XRD patterns and PL spectra of SRSO/SiO2 multilayers. (a) GI-XRD patterns measured for [2-nm-SRSO/SiO2]20 and [3-nm-SRSO/SiO2]20 multistacks annealed at 1,100°C for 60 min. Inset, PL spectra of the same MLs. The thickness of SRSO layer for each ML is mentioned in the figure. (b) PL properties of the [2-nm-SRSO/SiO2]20 ML versus annealing temperature; annealing time is 15 min.

Mentions: It is known that the high-temperature annealing at about 1,100°C is used to form Si-ncs required for optoelectronic application [9,11,23]. Grown MLs were annealed at 1,100°C for 60 min in nitrogen flow and were analyzed by means of XRD and PL methods to determine the formation and evolution of Si-ncs. XRD patterns taken in grazing geometry revealed the appearance of the Si-related (111) XRD peak at about 28° to 29° that confirmed the formation of Si-ncs inside the layers (Figure 2). As evident from the inset of Figure 2, the samples exhibit strong PL emission, which further confirms the formation of Si-ncs. The brightest emission was observed for the MLs with the 2-nm thickness of SRSO layer. The increase of the thickness of SRSO layer, leading to the increase of Si-ncs average size, results in the shift of PL peak position to the higher wavelength side (inset of Figure 2).


Hf-based high-k materials for Si nanocrystal floating gate memories.

Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F - Nanoscale Res Lett (2011)

XRD patterns and PL spectra of SRSO/SiO2 multilayers. (a) GI-XRD patterns measured for [2-nm-SRSO/SiO2]20 and [3-nm-SRSO/SiO2]20 multistacks annealed at 1,100°C for 60 min. Inset, PL spectra of the same MLs. The thickness of SRSO layer for each ML is mentioned in the figure. (b) PL properties of the [2-nm-SRSO/SiO2]20 ML versus annealing temperature; annealing time is 15 min.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3211225&req=5

Figure 2: XRD patterns and PL spectra of SRSO/SiO2 multilayers. (a) GI-XRD patterns measured for [2-nm-SRSO/SiO2]20 and [3-nm-SRSO/SiO2]20 multistacks annealed at 1,100°C for 60 min. Inset, PL spectra of the same MLs. The thickness of SRSO layer for each ML is mentioned in the figure. (b) PL properties of the [2-nm-SRSO/SiO2]20 ML versus annealing temperature; annealing time is 15 min.
Mentions: It is known that the high-temperature annealing at about 1,100°C is used to form Si-ncs required for optoelectronic application [9,11,23]. Grown MLs were annealed at 1,100°C for 60 min in nitrogen flow and were analyzed by means of XRD and PL methods to determine the formation and evolution of Si-ncs. XRD patterns taken in grazing geometry revealed the appearance of the Si-related (111) XRD peak at about 28° to 29° that confirmed the formation of Si-ncs inside the layers (Figure 2). As evident from the inset of Figure 2, the samples exhibit strong PL emission, which further confirms the formation of Si-ncs. The brightest emission was observed for the MLs with the 2-nm thickness of SRSO layer. The increase of the thickness of SRSO layer, leading to the increase of Si-ncs average size, results in the shift of PL peak position to the higher wavelength side (inset of Figure 2).

Bottom Line: Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures.The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated.The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures.

View Article: PubMed Central - HTML - PubMed

Affiliation: CIMAP, UMR CNRS/CEA/ENSICAEN/UCBN 6252, Ensicaen, 6 Bd Mal Juin, 14050 Caen Cedex 4, France. larysa.khomenkova@ensicaen.fr.

ABSTRACT
Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

No MeSH data available.


Related in: MedlinePlus