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Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

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Multibit mechanical logic circuits.(a) The response of the mechanical resonator measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and three pumps fpA=2f0+Δ, fpB=2f0−Δ and fpC=2f0+2Δ where Δ=0.5 Hz. (b) The corresponding numerical simulation except equation (9) is modified to include three pumps and two signals (Methods). (c) The 3-bit B∩(A∪C) logic circuit is constructed with the two second-order idlers fpB−(fpA−fs) and fpB−(fpC−fs) where Δs1=Δs2=0.5 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. (d) The A∪(B∩C) and (A∩B)∪(B∩C)∪(C∩A) logic circuits are constructed in parallel from first and second-order idlers fpA=fs, fpB−(fpC−fs) and three second-order idlers fpA−(fpB−fs), fpB−(fpC−fs) and fpC−(fpA−fs), respectively, with Δs1=0.5 Hz, Δs2=−1 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. In both cases, the mechanical parametric resonator was sampled via a spectrum analyser with an RBW=12.5 mHz. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and circuits have been colour coded.
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f4: Multibit mechanical logic circuits.(a) The response of the mechanical resonator measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and three pumps fpA=2f0+Δ, fpB=2f0−Δ and fpC=2f0+2Δ where Δ=0.5 Hz. (b) The corresponding numerical simulation except equation (9) is modified to include three pumps and two signals (Methods). (c) The 3-bit B∩(A∪C) logic circuit is constructed with the two second-order idlers fpB−(fpA−fs) and fpB−(fpC−fs) where Δs1=Δs2=0.5 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. (d) The A∪(B∩C) and (A∩B)∪(B∩C)∪(C∩A) logic circuits are constructed in parallel from first and second-order idlers fpA=fs, fpB−(fpC−fs) and three second-order idlers fpA−(fpB−fs), fpB−(fpC−fs) and fpC−(fpA−fs), respectively, with Δs1=0.5 Hz, Δs2=−1 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. In both cases, the mechanical parametric resonator was sampled via a spectrum analyser with an RBW=12.5 mHz. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and circuits have been colour coded.

Mentions: Beyond the implementation of fundamental two-bit logic gates, we also investigate the prospect of multibit logic circuits in a single mechanical resonator. To do this, a third pump is injected into the system at fpC=2f0+2Δ, which is used to encode a third-bit labelled as C. The resulting response of the system measured as above via gate 2 as a function of fs is shown in Figure 4a along with the corresponding theoretical response in Figure 4b (Methods).


Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

Multibit mechanical logic circuits.(a) The response of the mechanical resonator measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and three pumps fpA=2f0+Δ, fpB=2f0−Δ and fpC=2f0+2Δ where Δ=0.5 Hz. (b) The corresponding numerical simulation except equation (9) is modified to include three pumps and two signals (Methods). (c) The 3-bit B∩(A∪C) logic circuit is constructed with the two second-order idlers fpB−(fpA−fs) and fpB−(fpC−fs) where Δs1=Δs2=0.5 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. (d) The A∪(B∩C) and (A∩B)∪(B∩C)∪(C∩A) logic circuits are constructed in parallel from first and second-order idlers fpA=fs, fpB−(fpC−fs) and three second-order idlers fpA−(fpB−fs), fpB−(fpC−fs) and fpC−(fpA−fs), respectively, with Δs1=0.5 Hz, Δs2=−1 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. In both cases, the mechanical parametric resonator was sampled via a spectrum analyser with an RBW=12.5 mHz. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and circuits have been colour coded.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3105311&req=5

f4: Multibit mechanical logic circuits.(a) The response of the mechanical resonator measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and three pumps fpA=2f0+Δ, fpB=2f0−Δ and fpC=2f0+2Δ where Δ=0.5 Hz. (b) The corresponding numerical simulation except equation (9) is modified to include three pumps and two signals (Methods). (c) The 3-bit B∩(A∪C) logic circuit is constructed with the two second-order idlers fpB−(fpA−fs) and fpB−(fpC−fs) where Δs1=Δs2=0.5 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. (d) The A∪(B∩C) and (A∩B)∪(B∩C)∪(C∩A) logic circuits are constructed in parallel from first and second-order idlers fpA=fs, fpB−(fpC−fs) and three second-order idlers fpA−(fpB−fs), fpB−(fpC−fs) and fpC−(fpA−fs), respectively, with Δs1=0.5 Hz, Δs2=−1 Hz, ΔpA=0.25 Hz, ΔpB=−0.25 Hz and ΔpC=0.75 Hz. In both cases, the mechanical parametric resonator was sampled via a spectrum analyser with an RBW=12.5 mHz. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and circuits have been colour coded.
Mentions: Beyond the implementation of fundamental two-bit logic gates, we also investigate the prospect of multibit logic circuits in a single mechanical resonator. To do this, a third pump is injected into the system at fpC=2f0+2Δ, which is used to encode a third-bit labelled as C. The resulting response of the system measured as above via gate 2 as a function of fs is shown in Figure 4a along with the corresponding theoretical response in Figure 4b (Methods).

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Show MeSH