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Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

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Mechanical logic gates.(a) The mechanical resonator's response measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and two pump excitations at fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz. Using this response, an ∩ gate can be realized by any second-order idler (blue arrows), the ∪ gate can be realized via the degenerate first-order idler (green arrow) and the ⊕ gate can be realized via the degenerate idler at exactly fr=f0 (purple circle). (b) Two-bit binary input channels A and B can be encoded via fpA and fpB where the ∩ and ∪ logic gates can be realized by measuring the response of the mechanical resonator along the line 1 in a as a function of pump A and B, while both signal excitations are active. The resulting response measured via a spectrum analyser with a RBW of 25 mHz reveals both ∩ and ∪ gates in parallel in a single mechanical resonator. (c) The ⊕ gate can also be realized via the degenerate idler at exactly fr=f0 (purple circle in a) by varying the phase difference between s1 and s2, which can lead to both constructive and destructive interference. The destructive interference can be used to realize a ⊕ logic gate when φ=94° where the dots are from the experimental measurement and the line is the result of a numerical simulation (Methods). (d) The ⊕ gate is demonstrated along line 2 in a at fr=f0 by measuring the response of the mechanical resonator in a spectrum analyser with RBW=25 mHz as a function of pA and pB when the phase difference between s1 and s2 is 94° with an on/off ratio of 10:1. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and gates have been colour coded.
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f3: Mechanical logic gates.(a) The mechanical resonator's response measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and two pump excitations at fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz. Using this response, an ∩ gate can be realized by any second-order idler (blue arrows), the ∪ gate can be realized via the degenerate first-order idler (green arrow) and the ⊕ gate can be realized via the degenerate idler at exactly fr=f0 (purple circle). (b) Two-bit binary input channels A and B can be encoded via fpA and fpB where the ∩ and ∪ logic gates can be realized by measuring the response of the mechanical resonator along the line 1 in a as a function of pump A and B, while both signal excitations are active. The resulting response measured via a spectrum analyser with a RBW of 25 mHz reveals both ∩ and ∪ gates in parallel in a single mechanical resonator. (c) The ⊕ gate can also be realized via the degenerate idler at exactly fr=f0 (purple circle in a) by varying the phase difference between s1 and s2, which can lead to both constructive and destructive interference. The destructive interference can be used to realize a ⊕ logic gate when φ=94° where the dots are from the experimental measurement and the line is the result of a numerical simulation (Methods). (d) The ⊕ gate is demonstrated along line 2 in a at fr=f0 by measuring the response of the mechanical resonator in a spectrum analyser with RBW=25 mHz as a function of pA and pB when the phase difference between s1 and s2 is 94° with an on/off ratio of 10:1. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and gates have been colour coded.

Mentions: Next, to demonstrate the OR (∪) operation, the mechanical resonator is injected with two signals at fs1=f0+Δ+δ and fs2=f0−Δ+δ, which results in the reference vibrations being excited by both s1 and s2 (Supplementary Note 2 and Supplementary Figure S2). The complete set of idlers created when all the signals and pumps are activated is shown in Figure 3a. Activating only fpA yields two first-order idlers f0−δ (green arrow) and f0−δ+2Δ (black arrow A). Activating only fpB yields f0−δ−2Δ (red arrow B) and f0−δ (green arrow). From these measurements, it is seen that the f0−δ idler can be excited by either pump A or pump B, which enables the realization of the A∪B gate. The mechanical frequency response obtained at a fixed signal frequency (along line 1 in Fig. 3a) as a function of pump excitation is shown in Figure 3b and it clearly demonstrates the AND and OR operation. It should be emphasized that the two logic outputs can be obtained in parallel with only a single device in contrast to conventional logic devices where only sequential operation is available.


Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

Mechanical logic gates.(a) The mechanical resonator's response measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and two pump excitations at fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz. Using this response, an ∩ gate can be realized by any second-order idler (blue arrows), the ∪ gate can be realized via the degenerate first-order idler (green arrow) and the ⊕ gate can be realized via the degenerate idler at exactly fr=f0 (purple circle). (b) Two-bit binary input channels A and B can be encoded via fpA and fpB where the ∩ and ∪ logic gates can be realized by measuring the response of the mechanical resonator along the line 1 in a as a function of pump A and B, while both signal excitations are active. The resulting response measured via a spectrum analyser with a RBW of 25 mHz reveals both ∩ and ∪ gates in parallel in a single mechanical resonator. (c) The ⊕ gate can also be realized via the degenerate idler at exactly fr=f0 (purple circle in a) by varying the phase difference between s1 and s2, which can lead to both constructive and destructive interference. The destructive interference can be used to realize a ⊕ logic gate when φ=94° where the dots are from the experimental measurement and the line is the result of a numerical simulation (Methods). (d) The ⊕ gate is demonstrated along line 2 in a at fr=f0 by measuring the response of the mechanical resonator in a spectrum analyser with RBW=25 mHz as a function of pA and pB when the phase difference between s1 and s2 is 94° with an on/off ratio of 10:1. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and gates have been colour coded.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3105311&req=5

f3: Mechanical logic gates.(a) The mechanical resonator's response measured via the lock-in amplifier with two signal excitations at fs1=f0+Δ+δ and fs2=f0−Δ+δ and two pump excitations at fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz. Using this response, an ∩ gate can be realized by any second-order idler (blue arrows), the ∪ gate can be realized via the degenerate first-order idler (green arrow) and the ⊕ gate can be realized via the degenerate idler at exactly fr=f0 (purple circle). (b) Two-bit binary input channels A and B can be encoded via fpA and fpB where the ∩ and ∪ logic gates can be realized by measuring the response of the mechanical resonator along the line 1 in a as a function of pump A and B, while both signal excitations are active. The resulting response measured via a spectrum analyser with a RBW of 25 mHz reveals both ∩ and ∪ gates in parallel in a single mechanical resonator. (c) The ⊕ gate can also be realized via the degenerate idler at exactly fr=f0 (purple circle in a) by varying the phase difference between s1 and s2, which can lead to both constructive and destructive interference. The destructive interference can be used to realize a ⊕ logic gate when φ=94° where the dots are from the experimental measurement and the line is the result of a numerical simulation (Methods). (d) The ⊕ gate is demonstrated along line 2 in a at fr=f0 by measuring the response of the mechanical resonator in a spectrum analyser with RBW=25 mHz as a function of pA and pB when the phase difference between s1 and s2 is 94° with an on/off ratio of 10:1. All the spectra are offset for clarity and are numbered (roman numerals) to correlate with the numbered truth combinations in their corresponding truth tables where the various inputs and gates have been colour coded.
Mentions: Next, to demonstrate the OR (∪) operation, the mechanical resonator is injected with two signals at fs1=f0+Δ+δ and fs2=f0−Δ+δ, which results in the reference vibrations being excited by both s1 and s2 (Supplementary Note 2 and Supplementary Figure S2). The complete set of idlers created when all the signals and pumps are activated is shown in Figure 3a. Activating only fpA yields two first-order idlers f0−δ (green arrow) and f0−δ+2Δ (black arrow A). Activating only fpB yields f0−δ−2Δ (red arrow B) and f0−δ (green arrow). From these measurements, it is seen that the f0−δ idler can be excited by either pump A or pump B, which enables the realization of the A∪B gate. The mechanical frequency response obtained at a fixed signal frequency (along line 1 in Fig. 3a) as a function of pump excitation is shown in Figure 3b and it clearly demonstrates the AND and OR operation. It should be emphasized that the two logic outputs can be obtained in parallel with only a single device in contrast to conventional logic devices where only sequential operation is available.

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Show MeSH
Related in: MedlinePlus