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Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

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The mechanical idler dynamics.(a) The response of the mechanical oscillator measured via the lock-in amplifier with fp=2f0+Δ where Δ=0 Hz and fs=f0+δ reveals the fundamental mode fs and the idler fi=f0−δ. (b) The corresponding theoretical response generated from equation (9) (Methods). (c) The response of the mechanical oscillator measured via the lock-in amplifier, with fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz, and fs=f0+δ reveals, in addition to fs, the two first-order idlers  and  and two second-order idlers  that can be used to implement mechanical logic gates. (d) The corresponding numerical simulation except equation (9) is modified to include two pumps, and all the higher order idlers are labelled (Methods). In all cases, the experimental response is broader than the numerical simulations because of an experimental resolution band width (RBW) of 50 mHz.
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f2: The mechanical idler dynamics.(a) The response of the mechanical oscillator measured via the lock-in amplifier with fp=2f0+Δ where Δ=0 Hz and fs=f0+δ reveals the fundamental mode fs and the idler fi=f0−δ. (b) The corresponding theoretical response generated from equation (9) (Methods). (c) The response of the mechanical oscillator measured via the lock-in amplifier, with fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz, and fs=f0+δ reveals, in addition to fs, the two first-order idlers and and two second-order idlers that can be used to implement mechanical logic gates. (d) The corresponding numerical simulation except equation (9) is modified to include two pumps, and all the higher order idlers are labelled (Methods). In all cases, the experimental response is broader than the numerical simulations because of an experimental resolution band width (RBW) of 50 mHz.

Mentions: Parametric frequency conversion has an essential role in the execution of logic functions in this architecture and its operation is first described here1213. A pump with fixed frequency, fp=2f0, is injected into the 2DEG, while a signal at frequency fs=f0+δ, where δ is a variable, is applied to gate 1. The frequency response measured via gate 2 is shown in Figure 2a as a function of fs and the corresponding theoretical response is shown in Figure 2b (Methods). In addition to the input signal (blue arrow), an additional oscillation with a negative slope (green arrow) is observed. This excitation arises because of mixing between fp and fs resulting in the creation of an idler at fi=fp−fs=f0−δ, thus demonstrating mechanical parametric frequency conversion for the first time (Supplementary Note 1 and Supplementary Figure S1).


Interconnect-free parallel logic circuits in a single mechanical resonator.

Mahboob I, Flurin E, Nishiguchi K, Fujiwara A, Yamaguchi H - Nat Commun (2011)

The mechanical idler dynamics.(a) The response of the mechanical oscillator measured via the lock-in amplifier with fp=2f0+Δ where Δ=0 Hz and fs=f0+δ reveals the fundamental mode fs and the idler fi=f0−δ. (b) The corresponding theoretical response generated from equation (9) (Methods). (c) The response of the mechanical oscillator measured via the lock-in amplifier, with fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz, and fs=f0+δ reveals, in addition to fs, the two first-order idlers  and  and two second-order idlers  that can be used to implement mechanical logic gates. (d) The corresponding numerical simulation except equation (9) is modified to include two pumps, and all the higher order idlers are labelled (Methods). In all cases, the experimental response is broader than the numerical simulations because of an experimental resolution band width (RBW) of 50 mHz.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3105311&req=5

f2: The mechanical idler dynamics.(a) The response of the mechanical oscillator measured via the lock-in amplifier with fp=2f0+Δ where Δ=0 Hz and fs=f0+δ reveals the fundamental mode fs and the idler fi=f0−δ. (b) The corresponding theoretical response generated from equation (9) (Methods). (c) The response of the mechanical oscillator measured via the lock-in amplifier, with fpA=2f0+Δ and fpB=2f0−Δ where Δ=0.5 Hz, and fs=f0+δ reveals, in addition to fs, the two first-order idlers and and two second-order idlers that can be used to implement mechanical logic gates. (d) The corresponding numerical simulation except equation (9) is modified to include two pumps, and all the higher order idlers are labelled (Methods). In all cases, the experimental response is broader than the numerical simulations because of an experimental resolution band width (RBW) of 50 mHz.
Mentions: Parametric frequency conversion has an essential role in the execution of logic functions in this architecture and its operation is first described here1213. A pump with fixed frequency, fp=2f0, is injected into the 2DEG, while a signal at frequency fs=f0+δ, where δ is a variable, is applied to gate 1. The frequency response measured via gate 2 is shown in Figure 2a as a function of fs and the corresponding theoretical response is shown in Figure 2b (Methods). In addition to the input signal (blue arrow), an additional oscillation with a negative slope (green arrow) is observed. This excitation arises because of mixing between fp and fs resulting in the creation of an idler at fi=fp−fs=f0−δ, thus demonstrating mechanical parametric frequency conversion for the first time (Supplementary Note 1 and Supplementary Figure S1).

Bottom Line: This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds.A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable.Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

View Article: PubMed Central - PubMed

Affiliation: NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, Kanagawa 243-0198, Japan. imran@will.brl.ntt.co.jp

ABSTRACT
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Show MeSH
Related in: MedlinePlus