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Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics.

Henkel C, Abermann S, Bethge O, Pozzovivo G, Klang P, Stöger-Pollach M, Bertagnolli E - Microelectron Eng (2011)

Bottom Line: As a mid-gap metal gate electrode TiN capped with W is applied.Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance.As a result, the overall thermal load was kept as low as 350, 400 or 500 °C.

View Article: PubMed Central - PubMed

Affiliation: Vienna University of Technology, Institute for Solid State Electronics, Vienna 1040, Austria.

ABSTRACT
Schottky barrier SOI-MOSFETs incorporating a La(2)O(3)/ZrO(2) high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10(11) eV(-1) cm(-2), a low subthreshold slope of 70-80 mV/decade, and an I(ON)/I(OFF) current ratio greater than 2 × 10(6) are obtained.

No MeSH data available.


Related in: MedlinePlus

Output characteristics of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric, whereat a PDA at 350 °C and a PMA at 500 °C are applied. For small drain voltages a linear current drive is obtained. UG is swept from 0 V to −2 V in −0.2 V steps.
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f0035: Output characteristics of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric, whereat a PDA at 350 °C and a PMA at 500 °C are applied. For small drain voltages a linear current drive is obtained. UG is swept from 0 V to −2 V in −0.2 V steps.

Mentions: Considering the specific performance of devices subjected to a PDA at 350 °C and a PMA at 500 °C a subthreshold swing of 71 mV/decade close to the thermal limit of 60 mV/decade is obtained at room temperature, as well as an excellent ION/IOFF current ratio greater than 2 × 106, obtained for UDS = −1 V. For the 2 μm printed gate length the highest transconductance measured is 25 μS/μm. The threshold voltage, obtained from a linear fit of the drain current as a function of the gate voltage for small drain to source voltages amounts to Uth = −0.43 V for the given device. The inverse subthreshold slope of the n-branch amounts to 260 mV/decade for UDS = −1.5 V. Fig. 6a shows the drive current obtained at UG = −2 V and UDS = −1.5 V as a function of the printed gate length. The linear relationship demonstrates the excellent scalability of the developed low temperature process scheme for ALD La2O3/ZrO2 gate dielectrics. Comparing the results to a PMA performed at 350 °C, whereat a smaller ION/IOFF current ratio is obtained due to the increased current contribution from the reverse current of the drain Schottky diode structure, the highest ION/IOFF ration is achieved for a PMA applied at 500 °C (Fig. 6b). However, smallest gate oxide leakage current (see Fig. 4b) was obtained from PMA temperatures lower than 500 °C. Especially for thinner gate oxide thicknesses this increase in the gate oxide leakage current would affect the ION/IOFF current ratio. Thus this trade-off may be best solved by applying a PMA at 400 °C. As shown in the output characteristics in Fig. 7, no sublinear current drive for small drain voltages is visible.


Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics.

Henkel C, Abermann S, Bethge O, Pozzovivo G, Klang P, Stöger-Pollach M, Bertagnolli E - Microelectron Eng (2011)

Output characteristics of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric, whereat a PDA at 350 °C and a PMA at 500 °C are applied. For small drain voltages a linear current drive is obtained. UG is swept from 0 V to −2 V in −0.2 V steps.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3065308&req=5

f0035: Output characteristics of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric, whereat a PDA at 350 °C and a PMA at 500 °C are applied. For small drain voltages a linear current drive is obtained. UG is swept from 0 V to −2 V in −0.2 V steps.
Mentions: Considering the specific performance of devices subjected to a PDA at 350 °C and a PMA at 500 °C a subthreshold swing of 71 mV/decade close to the thermal limit of 60 mV/decade is obtained at room temperature, as well as an excellent ION/IOFF current ratio greater than 2 × 106, obtained for UDS = −1 V. For the 2 μm printed gate length the highest transconductance measured is 25 μS/μm. The threshold voltage, obtained from a linear fit of the drain current as a function of the gate voltage for small drain to source voltages amounts to Uth = −0.43 V for the given device. The inverse subthreshold slope of the n-branch amounts to 260 mV/decade for UDS = −1.5 V. Fig. 6a shows the drive current obtained at UG = −2 V and UDS = −1.5 V as a function of the printed gate length. The linear relationship demonstrates the excellent scalability of the developed low temperature process scheme for ALD La2O3/ZrO2 gate dielectrics. Comparing the results to a PMA performed at 350 °C, whereat a smaller ION/IOFF current ratio is obtained due to the increased current contribution from the reverse current of the drain Schottky diode structure, the highest ION/IOFF ration is achieved for a PMA applied at 500 °C (Fig. 6b). However, smallest gate oxide leakage current (see Fig. 4b) was obtained from PMA temperatures lower than 500 °C. Especially for thinner gate oxide thicknesses this increase in the gate oxide leakage current would affect the ION/IOFF current ratio. Thus this trade-off may be best solved by applying a PMA at 400 °C. As shown in the output characteristics in Fig. 7, no sublinear current drive for small drain voltages is visible.

Bottom Line: As a mid-gap metal gate electrode TiN capped with W is applied.Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance.As a result, the overall thermal load was kept as low as 350, 400 or 500 °C.

View Article: PubMed Central - PubMed

Affiliation: Vienna University of Technology, Institute for Solid State Electronics, Vienna 1040, Austria.

ABSTRACT
Schottky barrier SOI-MOSFETs incorporating a La(2)O(3)/ZrO(2) high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10(11) eV(-1) cm(-2), a low subthreshold slope of 70-80 mV/decade, and an I(ON)/I(OFF) current ratio greater than 2 × 10(6) are obtained.

No MeSH data available.


Related in: MedlinePlus