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Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics.

Henkel C, Abermann S, Bethge O, Pozzovivo G, Klang P, Stöger-Pollach M, Bertagnolli E - Microelectron Eng (2011)

Bottom Line: As a mid-gap metal gate electrode TiN capped with W is applied.Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance.As a result, the overall thermal load was kept as low as 350, 400 or 500 °C.

View Article: PubMed Central - PubMed

Affiliation: Vienna University of Technology, Institute for Solid State Electronics, Vienna 1040, Austria.

ABSTRACT
Schottky barrier SOI-MOSFETs incorporating a La(2)O(3)/ZrO(2) high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10(11) eV(-1) cm(-2), a low subthreshold slope of 70-80 mV/decade, and an I(ON)/I(OFF) current ratio greater than 2 × 10(6) are obtained.

No MeSH data available.


Related in: MedlinePlus

Leakage current density obtained from MOS capacitors. In (a) different PDA treatments are performed but same PMA treatments are applied. In (b) the PDA is applied at 350 °C but different PMA treatments are performed. From (c) the interface trap density can be found comparing these respective PMA treatments.
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f0020: Leakage current density obtained from MOS capacitors. In (a) different PDA treatments are performed but same PMA treatments are applied. In (b) the PDA is applied at 350 °C but different PMA treatments are performed. From (c) the interface trap density can be found comparing these respective PMA treatments.

Mentions: Comparing three different PDA treatments of the ∼7 nm thick La2O3/ZrO2 film, an increase in the leakage current density, measured in the accumulation regime (at + 1 V), as shown in Fig. 4a, is found for fixed PMA temperatures of 350 °C and 400 °C. Here, an excellent leakage current density level of 15 μA/cm2 is found for the lowest PDA temperatures of 350 °C. Varying the different PMA treatments (Fig. 4b), the leakage current density is the lowest for a PMA at 350 °C, and is increasing to a value of 55 mA/cm2 for a PMA treatment at temperatures of 500 °C. This temperature dependence is most likely due to the increased crystallization of the stacked La2O3/ZrO2 layer observed, and the correlated leakage current along possible grain boundaries in the crystalline phase. The presence of crystalline inclusion may additionally affect the device performance of short channel devices, due to the variation of the dielectric constant of the oxide along the channel of the MOSFET. The variation depends on the size of crystalline inclusions and the crystalline orientations of the grains. This becomes even more important as for tetragonal ZrO2 additionally an anisotropic dielectric constant with 41.6 in the x- and y-direction is observed while a value of 14.9 is observed in the z-axis (c-direction) [20].


Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics.

Henkel C, Abermann S, Bethge O, Pozzovivo G, Klang P, Stöger-Pollach M, Bertagnolli E - Microelectron Eng (2011)

Leakage current density obtained from MOS capacitors. In (a) different PDA treatments are performed but same PMA treatments are applied. In (b) the PDA is applied at 350 °C but different PMA treatments are performed. From (c) the interface trap density can be found comparing these respective PMA treatments.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3065308&req=5

f0020: Leakage current density obtained from MOS capacitors. In (a) different PDA treatments are performed but same PMA treatments are applied. In (b) the PDA is applied at 350 °C but different PMA treatments are performed. From (c) the interface trap density can be found comparing these respective PMA treatments.
Mentions: Comparing three different PDA treatments of the ∼7 nm thick La2O3/ZrO2 film, an increase in the leakage current density, measured in the accumulation regime (at + 1 V), as shown in Fig. 4a, is found for fixed PMA temperatures of 350 °C and 400 °C. Here, an excellent leakage current density level of 15 μA/cm2 is found for the lowest PDA temperatures of 350 °C. Varying the different PMA treatments (Fig. 4b), the leakage current density is the lowest for a PMA at 350 °C, and is increasing to a value of 55 mA/cm2 for a PMA treatment at temperatures of 500 °C. This temperature dependence is most likely due to the increased crystallization of the stacked La2O3/ZrO2 layer observed, and the correlated leakage current along possible grain boundaries in the crystalline phase. The presence of crystalline inclusion may additionally affect the device performance of short channel devices, due to the variation of the dielectric constant of the oxide along the channel of the MOSFET. The variation depends on the size of crystalline inclusions and the crystalline orientations of the grains. This becomes even more important as for tetragonal ZrO2 additionally an anisotropic dielectric constant with 41.6 in the x- and y-direction is observed while a value of 14.9 is observed in the z-axis (c-direction) [20].

Bottom Line: As a mid-gap metal gate electrode TiN capped with W is applied.Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance.As a result, the overall thermal load was kept as low as 350, 400 or 500 °C.

View Article: PubMed Central - PubMed

Affiliation: Vienna University of Technology, Institute for Solid State Electronics, Vienna 1040, Austria.

ABSTRACT
Schottky barrier SOI-MOSFETs incorporating a La(2)O(3)/ZrO(2) high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10(11) eV(-1) cm(-2), a low subthreshold slope of 70-80 mV/decade, and an I(ON)/I(OFF) current ratio greater than 2 × 10(6) are obtained.

No MeSH data available.


Related in: MedlinePlus