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Record Endurance for Single-Walled Carbon Nanotube-Based Memory Cell.

Di Bartolomeo A, Yang Y, Rinzan MB, Boyd AK, Barbara P - Nanoscale Res Lett (2010)

Bottom Line: We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO(2)/nanotube interface.We show that this type of memory device is robust, withstanding over 10(5) operating cycles, with a current drive capability up to 10(-6) A at 20 mV drain bias, thus competing with state-of-the-art Si-devices.We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

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ABSTRACT
We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO(2)/nanotube interface. We show that this type of memory device is robust, withstanding over 10(5) operating cycles, with a current drive capability up to 10(-6) A at 20 mV drain bias, thus competing with state-of-the-art Si-devices. We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

No MeSH data available.


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a Effect of low temperature on the transfer characteristic of the SWCNT transistor. Low temperature greatly increases the ON/OFF ratio and slightly reduces the hysteresis width. b Erase-read-write-read cycles of the SWCNT memory device with ± 20 V and 0.25 s pulses. A negative pulse pushes the memory in the OFF state, while a positive pulse pulls it in the ON state. c Endurance tests performed by cycling at 77 K and in vacuum. d Retention of states under continuous reading in air (blue triangle), at low pressure (black box), and at low pressure and temperature (red circle). The same device has better retention at low pressure, and the retention is further improved at low temperature which produces a larger separation between the ON and OFF states. Current corresponding to each state was measured at 1-s intervals
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Figure 2: a Effect of low temperature on the transfer characteristic of the SWCNT transistor. Low temperature greatly increases the ON/OFF ratio and slightly reduces the hysteresis width. b Erase-read-write-read cycles of the SWCNT memory device with ± 20 V and 0.25 s pulses. A negative pulse pushes the memory in the OFF state, while a positive pulse pulls it in the ON state. c Endurance tests performed by cycling at 77 K and in vacuum. d Retention of states under continuous reading in air (blue triangle), at low pressure (black box), and at low pressure and temperature (red circle). The same device has better retention at low pressure, and the retention is further improved at low temperature which produces a larger separation between the ON and OFF states. Current corresponding to each state was measured at 1-s intervals

Mentions: Figure 2a shows the transfer characteristics of a device, displaying an ambipolar behaviour as a consequence of the small channel bandgap. At room temperature (blue triangle), the CNFET exhibits a small ON/OFF current ratio (≤10) and a low ON-state resistance (~20 kΩ) saturating at large negative voltage, confirming the high transparency of the contacts. The low ON/OFF ratio is due to the small SWCNT bandgap and can be enhanced by selecting a semiconducting SWCNT with smaller diameter and large bandgap. In our previous work [15,17], we obtained devices with low contact resistance and large ON/OFF ratio, with the same fabrication process used for the samples discussed here. Because we use nanotubes with a small bandgap, we can test memory device properties for the same sample, with very different values of ON/OFF ratio, i.e. smaller ON/OFF ratio at room temperature or larger ON/OFF ratio at low temperature. Indeed, at low temperature (red circles), the ON/OFF ratio increases considerably: the current in the OFF state decreases and the current in the ON state increases. The increase in the ON-state current is due to reduced phonon scattering [18,19]. The ON-state current of ~10−6 A for a drain bias as low as 20 mV shows that the CNFET has a higher current drive capability than the present sub-micron Si-based devices [16,20].


Record Endurance for Single-Walled Carbon Nanotube-Based Memory Cell.

Di Bartolomeo A, Yang Y, Rinzan MB, Boyd AK, Barbara P - Nanoscale Res Lett (2010)

a Effect of low temperature on the transfer characteristic of the SWCNT transistor. Low temperature greatly increases the ON/OFF ratio and slightly reduces the hysteresis width. b Erase-read-write-read cycles of the SWCNT memory device with ± 20 V and 0.25 s pulses. A negative pulse pushes the memory in the OFF state, while a positive pulse pulls it in the ON state. c Endurance tests performed by cycling at 77 K and in vacuum. d Retention of states under continuous reading in air (blue triangle), at low pressure (black box), and at low pressure and temperature (red circle). The same device has better retention at low pressure, and the retention is further improved at low temperature which produces a larger separation between the ON and OFF states. Current corresponding to each state was measured at 1-s intervals
© Copyright Policy
Related In: Results  -  Collection

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getmorefigures.php?uid=PMC2964474&req=5

Figure 2: a Effect of low temperature on the transfer characteristic of the SWCNT transistor. Low temperature greatly increases the ON/OFF ratio and slightly reduces the hysteresis width. b Erase-read-write-read cycles of the SWCNT memory device with ± 20 V and 0.25 s pulses. A negative pulse pushes the memory in the OFF state, while a positive pulse pulls it in the ON state. c Endurance tests performed by cycling at 77 K and in vacuum. d Retention of states under continuous reading in air (blue triangle), at low pressure (black box), and at low pressure and temperature (red circle). The same device has better retention at low pressure, and the retention is further improved at low temperature which produces a larger separation between the ON and OFF states. Current corresponding to each state was measured at 1-s intervals
Mentions: Figure 2a shows the transfer characteristics of a device, displaying an ambipolar behaviour as a consequence of the small channel bandgap. At room temperature (blue triangle), the CNFET exhibits a small ON/OFF current ratio (≤10) and a low ON-state resistance (~20 kΩ) saturating at large negative voltage, confirming the high transparency of the contacts. The low ON/OFF ratio is due to the small SWCNT bandgap and can be enhanced by selecting a semiconducting SWCNT with smaller diameter and large bandgap. In our previous work [15,17], we obtained devices with low contact resistance and large ON/OFF ratio, with the same fabrication process used for the samples discussed here. Because we use nanotubes with a small bandgap, we can test memory device properties for the same sample, with very different values of ON/OFF ratio, i.e. smaller ON/OFF ratio at room temperature or larger ON/OFF ratio at low temperature. Indeed, at low temperature (red circles), the ON/OFF ratio increases considerably: the current in the OFF state decreases and the current in the ON state increases. The increase in the ON-state current is due to reduced phonon scattering [18,19]. The ON-state current of ~10−6 A for a drain bias as low as 20 mV shows that the CNFET has a higher current drive capability than the present sub-micron Si-based devices [16,20].

Bottom Line: We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO(2)/nanotube interface.We show that this type of memory device is robust, withstanding over 10(5) operating cycles, with a current drive capability up to 10(-6) A at 20 mV drain bias, thus competing with state-of-the-art Si-devices.We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

View Article: PubMed Central - HTML - PubMed

ABSTRACT
We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO(2)/nanotube interface. We show that this type of memory device is robust, withstanding over 10(5) operating cycles, with a current drive capability up to 10(-6) A at 20 mV drain bias, thus competing with state-of-the-art Si-devices. We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

No MeSH data available.


Related in: MedlinePlus